This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

10

EN25F40

Rev. B, Issue Date: 2007/05/09

Read Status Register (RDSR) (05h)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register

may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When

one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before

sending a new instruction to the device. It is also possible to read the Status Register continuously, as

shown in Figure 7.

Table 6. Status Register Bit Locations

The status and control bits of the Status Register are as follows:

WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such

cycle is in progress.

WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When

set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and

no Write Status Register, Program or Erase instruction is accepted.

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the

area to be software protected against Program and Erase instructions. These bits are written with the

Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is

set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP)

Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect (BP2, BP1, BP0) bits can be

written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) instruction is

executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0.