This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

8

EN25F20

Rev. B, Issue Date: 2007/05/15

All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase

cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues

unaffected.

Table 4. Instruction Set

Instruction Name

Byte 1

Code

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

n-Bytes

Write Enable

06h

Write Disable / Exit

OTP mode

04h

Read Status

Register

05h

(S7-S0)(1)

continuous

(2)

Write Status

Register

01h

S7-S0

Read Data

03h

A23-A16

A15-A8

A7-A0

(D7-D0)

(Next byte)

continuous

Fast Read

0Bh

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)

(Next Byte)

continuous

Page Program

02h

A23-A16

A15-A8

A7-A0

D7-D0

(Next byte)

continuous

Sector Erase

20h

A23-A16

A15-A8

A7-A0

Block Erase

D8h/ 52h

A23-A16

A15-A8

A7-A0

Chip Erase

C7h/ 60h

Deep Power-down

B9h

Release from Deep

Power-down, and

read Device ID

dummy

dummy

dummy

(ID7-ID0)

(4)

Release from Deep

Power-down

ABh

Manufacturer/

Device ID

90h

dummy

dummy

00h(5)

(M7-M0)

(ID7-ID0)

Read Identification

9Fh

(M7-M0)

(ID15-ID8)

(ID7-ID0)

Enter OTP mode

3Ah

Notes:

1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from

the device on the DO pin.

2. The Status Register contents will repeat continuously until CS# terminate the instruction.

3. All sectors may use any address within the sector.

4. The Device ID will repeat continuously until CS# terminate the instruction.

5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.

00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.

Table 5. Manufacturer and Device Identification

OP Code

(M7-M0)

(ID15-ID0)

(ID7-ID0)

ABh

11h

90h

1Ch

11h

9Fh

1Ch

3112h

Write Enable (WREN) (06h)

The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write Enable

Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip

Erase (CE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction

code, and then driving Chip Select (CS#) High.