11/16

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Method to cancel each command

○

READ

・

Method to cancel : cancel by CSB = “H”

○

RDSR

・

Method to cancel : cancel by CSB = “H”

○

WRITE、PAGE WRITE

a：Ope code, address input area.

Cancellation is available by CSB=”H”

b：Data input area (D7~D1 input area)

Cancellation is available by CSB=”H”

c：Data input area (D0 area)

When CSB is started, write starts.

After CSB rise, cancellation cannot be made by any means.

d：tE/W area.

Cancellation is available by CSB = “H”. However, when

write starts (CSB is started) in the area c, cancellation

cannot be made by any means. And by inputting on

SCK clock, cancellation cannot be made. In page write

mode, there is write enable area at every 8 clocks.

Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore

write it once again.

Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,

therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.

○

WRSR

a：From ope code to 15 rise.

Cancel by CSB =”H”.

b：From 15 clock rise to 16 clock rise (write enable area).

When CSB is started, write starts.

After CSB rise, cancellation cannot be made by any means.

c：After 16 clock rise.

Cancel by CSB=”H”. However, when write starts (CSB is started)

in the area b, cancellation cannot be made by any means.

And, by inputting on SCK clock, cancellation cannot be made.

Note 1) If Vcc is made OFF during write execution, designated address data is not guaranteed, therefore write it once

again

Note 2) If CSB is started at the same timing as that of the SCK rise, write execution / cancel becomes unstable,

therefore, it is recommended to fall in SCK = “L” area. As for SCK rise, assure timing of tCSS / tCSH or higher.

○

WREN/WRDI

a：From ope code to 7-th clock rise, cancel by CSB = “H”.

b：Cancellation is not available when CSB is started after 7-th clock.

Ope code

Address

Cancel available in all areas of read mode

Data

8 bit

8 bit/16bit

8 bit

Fig.46 READ cancel valid timing

Ope code

Cancel available in all

areas of read mode

Data

8 bit

8 bit

Fig.47 RDSR cancel valid timing

Ope code

Address

a

Data

tE/W

b

d

c

8bit

8bit/16bit

8bit

D7

b

D6

D5

D4

D3

D2

D1

D0

SCK

SI

c

Ope code

Data

tE/W

8 bit

14

15

16

17

D1

D0

a

b

c

8 bit

a

b

c

Ope code

8 bit

7

8

9

a

b

a

b

SCK

Fig.49 WRSR cancel valid timing

Fig.50 WREN/WRDI cancel valid timing

Fig.48 WRITE cancel valid timing