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HYS72T256220HP-3S-B Datasheet(PDF) 21 Page - Qimonda AG |
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HYS72T256220HP-3S-B Datasheet(HTML) 21 Page - Qimonda AG |
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21 / 65 page  Internet Data Sheet Rev. 1.1, 2007-03 21 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM TABLE 16 DRAM Component Timing Parameter by Speed Grade - DDR2–667 Parameter Symbol DDR2–667 Unit Note1)2)3)4)5)6)7) 8) Min. Max. DQ output access time from CK / CK t AC –450 +450 ps 9) CAS to CAS command delay t CCD 2— nCK — Average clock high pulse width t CH.AVG 0.48 0.52 t CK.AVG 10)11) Average clock period t CK.AVG 3000 8000 ps — CKE minimum pulse width ( high and low pulse width) t CKE 3— nCK 12) Average clock low pulse width t CL.AVG 0.48 0.52 t CK.AVG 10)11) Auto-Precharge write recovery + precharge time t DAL WR + t nRP —nCK 13)14) Minimum time clocks remain ON after CKE asynchronously drops LOW t DELAY t IS + tCK .AVG + t IH –– ns DQ and DM input hold time t DH.BASE 175 –– ps 19)20)15) DQ and DM input pulse width for each input t DIPW 0.35 — t CK.AVG — DQS output access time from CK / CK t DQSCK –400 +400 ps 9) DQS input high pulse width t DQSH 0.35 — t CK.AVG — DQS input low pulse width t DQSL 0.35 — t CK.AVG — DQS-DQ skew for DQS & associated DQ signals t DQSQ — 240 ps 16) DQS latching rising transition to associated clock edges t DQSS – 0.25 + 0.25 t CK.AVG 17) DQ and DM input setup time t DS.BASE 100 –– ps 18)19)20) DQS falling edge hold time from CK t DSH 0.2 — t CK.AVG 17) DQS falling edge to CK setup time t DSS 0.2 — t CK.AVG 17) CK half pulse width t HP Min ( t CH.ABS, t CL.ABS) __ ps 21) Data-out high-impedance time from CK / CK t HZ — t AC.MAX ps 9)22) Address and control input hold time t IH.BASE 275 — ps 25)23) Control & address input pulse width for each input t IPW 0.6 — t CK.AVG — Address and control input setup time t IS.BASE 200 — ps 24)25) DQ low impedance time from CK/CK t LZ.DQ 2x t AC.MIN t AC.MAX ps 9)22) DQS/DQS low-impedance time from CK / CK t LZ.DQS t AC.MIN t AC.MAX ps 9)22) MRS command to ODT update delay t MOD 012 ns 31) Mode register set command cycle time t MRD 2— nCK — OCD drive mode output delay t OIT 012 ns 31) DQ/DQS output hold time from DQS t QH t HP – tQHS —ps 26) DQ hold skew factor t QHS — 340 ps 27) Read preamble t RPRE 0.9 1.1 t CK.AVG 28)29) Read postamble t RPST 0.4 0.6 t CK.AVG 28)30) Internal Read to Precharge command delay t RTP 7.5 — ns 31) Write preamble t WPRE 0.35 — t CK.AVG — |
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Similar Description - HYS72T256220HP-3S-B |
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