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ADS8515

SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

ADS8515I

ADS8515IB

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

Full-scale

-0.5

0.5

-0.25

0.25

Int. Ref.

%FSR

error

(3) (4)

Full-scale error drift

Int. Ref.

±7

±7

ppm/

°C

Full-scale

-0.25

0.25

-0.1

0.1

Ext. 4.096-V Ref.

%FSR

error

(3) (4)

Full-scale error drift

Ext. 4.096-V Ref.

±2

±2

ppm/

°C

Bipolar zero error

(3)

-4

4

-2

2

mV

Bipolar zero error drift

±2

±2

ppm/

°C

Power supply sensitivity

-8

8

-8

8

LSB

AC ACCURACY

SFDR

Spurious-free dynamic range

95

102

97

102

dB

(5)

THD

Total harmonic distortion

-100

-94

-100

-96

dB

87

91

89

91

dB

SINAD

Signal-to-(noise+distortion)

–60-dB Input

30

32

dB

SNR

Signal-to-noise ratio

88

92

90

92

dB

Full-power bandwidth

(6)

500

500

kHz

SAMPLING DYNAMICS

Aperture delay

5

5

ns

Transient response

FS Step

2

2

µs

Overvoltage recovery

(7)

150

150

ns

REFERENCE

Internal reference voltage

4.076

4.096

4.116

4.076

4.096

4.116

V

Internal reference source current (must

1

1

µA

use external buffer)

Internal reference drift

8

8

ppm/

°C

External reference voltage range for

3.9

4.096

4.2

3.9

4.096

4.2

V

specified linearity

External reference current drain

Ext. 4.096-V Ref.

100

100

µA

DIGITAL INPUTS

Logic levels

Low-level input voltage

-0.3

0.8

-0.3

V

High-level input voltage

V

Low-level input current

±10

±10

µA

High-level input current

±10

±10

µA

DIGITAL OUTPUTS

Data format (Parallel 16-bits)

Data coding (Binary 2's complement)

Low-level output voltage

0.4

0.4

V

High-level output voltage

0.8

×V

DIG

0.8

×V

DIG

V

Hi-Z state,

±5

±5

µA

Leakage current

Output capacitance

Hi-Z state

15

15

pF

DIGITAL TIMING

Bus access timing

83

83

ns

Bus relinquish timing

83

83

ns

POWER SUPPLIES

(3)

As measured with fixed resistors shown in Figure 22. Adjustable to zero with external potentiometer.

(4)

Full-scale error is the worst case of -full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transition

voltage (not divided by the full-scale range) and includes the effect of offset error.

(5)

All specifications in dB are referred to a full-scale ±10-V input.

(6)

Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB, or 10 bits of

accuracy.

(7)

Recovers to specified performance after 2 x FS input overvoltage.

Copyright © 2007, Texas Instruments Incorporated

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