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HYS72T1G242EP-3.7-C Datasheet(PDF) 5 Page - Qimonda AG |
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HYS72T1G242EP-3.7-C Datasheet(HTML) 5 Page - Qimonda AG |
5 / 43 page Internet Data Sheet Rev. 1.0, 2007-07 5 07242007-LR08-OZC0 HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C Registerd DDR2 SDRAM Module 2 Pin Configuration and Block Diagrams This chapter contains the pin configuration and block diagrams. 2.1 Pin Configuration The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1. TABLE 5 Pin Configuration of RDIMM Pin No. Name Pin Type Buffer Type Function Clock Signals 185 CK0 I SSTL Clock Signal CK0, Complementary Clock Signal CK0 The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. 186 CK0 ISSTL 52 CKE0 I SSTL Clock Enables 1:0 Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE0 initiates the Power Down Mode or the Self Refresh Mode. Note: 2-Ranks module 171 CKE1 I SSTL NC NC — Not Connected Note: 1-Rank module Control Signals 193 S0 ISSTL Chip Select Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0 Rank 1 is selected by S1 The input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When S is HIGH, all register outputs (except CK, ODT and Chip select) remain in the previous state. Note: 2-Ranks module 76 S1 ISSTL NC NC — Not Connected Note: 1-Rank module |
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