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HYB18T512400BF Datasheet(PDF) 4 Page - Qimonda AG |
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HYB18T512400BF Datasheet(HTML) 4 Page - Qimonda AG |
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4 / 47 page  HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B Fully-Buffered DDR2 SDRAM Modules Internet Data Sheet Rev.1.01, 2007-06-20 4 10062006-RQWY-GI6S 1.2 Description This document describes the electrical and mechanical features of a 240-pin, PC2-4200F, PC2-5300F, ECC type, Fully Buffered Double-Data-Rate Two Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs). Fully Buffered DIMMs use commodity DRAMs isolated from the memory channel behind a buffer on the DIMM. They are intended for use as main memory when installed in systems such as servers and workstations. PC2-4200F, PC2-5300F, refers to the DIMM naming convention indicating the DDR2 SDRAMs running at 266, 333, MHz clock speed and offering 4200, 5300, MB/s peak bandwidth. FB-DIMM features a novel architecture including the Advanced Memory Buffer. This single chip component, located in the center of each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the DDR2 SDRAMs including data in- and output. The AMB communicates with the host controller and / or the adjacent DIMMs on a system board using an Industry Standard High-Speed Differential Point-to-Point Link Interface at 1.5 V. The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The Advanced Memory Buffer interface is responsible for handling channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the memory channel. Fully Buffered DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. The maximum memory capacity is 288 DDR2 SDRAM devices per channel or 8 DIMMs. Min. Row Active Time t RAS 45 45 45 ns Min. Row Cycle Time t RC 60 60 60 ns QAG Speed Code –2.5 –3S –3.7 Unit DRAM Speed Grade DDR2–800E DDR2–667D DDR2–533C Module Speed Grade PC2–6400E PC2–5300D PC2–4200C CAS-RCD-RP latencies 6–6–6 5–5–5 4–4–4 |
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