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HYS64T128020EML-3S-B Datasheet(PDF) 5 Page - Qimonda AG |
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HYS64T128020EML-3S-B Datasheet(HTML) 5 Page - Qimonda AG |
5 / 39 page Preliminary Internet Data Sheet Rev. 0.5, 2007-05 5 05212007-7F24-MITO HYS64T128020EML-[3S/3.7/5]-B Unbuffered DDR2 SDRAM MicroDIMM Modules 2 Pin Configuration and Block Diagrams This chapter contains the pin configuration and block diagrams. 2.1 Pin Configuration The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in Table 4 (214 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Figure 1. TABLE 4 Pin Configuration of MDIMM Ball No. Name Pin Type Buffer Type Function Clock Signals 122 CK0 I SSTL Clock Signal CK 1:0, Complementary Clock Signal CK 1:0 Note: The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. 194 CK1 I SSTL 123 CK0 I SSTL 195 CK1 I SSTL 43 CKE0 I SSTL Clock Enables 1:0 Note: Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE0 initiates the Power Down Mode or the Self Refresh Mode. 1. 2-rank module 147 CKE1 I SSTL NC NC Not Connected Note: 1-rank module Control Signals 165 S0 I SSTL Chip Select Rank 1:01)2) 62 S1 I SSTL NC NC Not Connected Note: 1-rank module 163 RAS I Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Note: When sampled at the cross point of the rising edge of CK,and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. 60 CAS I SSTL 56 WE I SSTL Address Signals 55 BA0 I SSTL Bank Address Bus 1:0 Note: Select internal SDRAM memory bank 162 BA1 I SSTL |
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