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HYB18TC1G160AF Datasheet(PDF) 6 Page - Qimonda AG |
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HYB18TC1G160AF Datasheet(HTML) 6 Page - Qimonda AG |
6 / 54 page Internet Data Sheet Rev. 1.11, 2006-09 6 03292006-PJAE-UQLG HYB18TC1G[80/16]0AF 1-Gbit DDR2 SDRAM 2 Pin Configuration This chapter contains the pin configuration. 2.1 Pin Configuration for TFBGA–68 The pin configuration of a DDR2 SDRAM is listed by function in Table 5. The abbreviations used in the Pin# and Buffer Type columns are explained in Table 6 and Table 7 respectively. The pin numbering for the FBGA package is depicted in Figure 1 for ×8 components. TABLE 5 Pin Configuration of DDR2 SDRAM Ball#/Pin# Name Pin Type Buffer Type Function Clock Signals ×8 Organizations J8 CK I SSTL Clock Signal CK, Complementary Clock Signal CK K8 CK I SSTL K2 CKE I SSTL Clock Enable Control Signals ×8 Organizations K7 RAS I SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) L7 CAS I SSTL K3 WE I SSTL L8 CS I SSTL Chip Select Address Signals ×8 Organizations L2 BA0 I SSTL Bank Address Bus 2:0 L3 BA1 I SSTL L1 BA2 I SSTL M8 A0 I SSTL Address Signal 12:0, Address Signal 10/Autoprecharge M3 A1 I SSTL M7 A2 I SSTL N2 A3 I SSTL N8 A4 I SSTL N3 A5 I SSTL N7 A6 I SSTL P2 A7 I SSTL P8 A8 I SSTL P3 A9 I SSTL M2 A10 I SSTL AP I SSTL P7 A11 I SSTL R2 A12 I SSTL |
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