HYB18TC256160AF-3.7 datasheet(3/54 Pages) QIMONDA

Part #	HYB18TC256160AF-3.7

Description	256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

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Manufacturer	QIMONDA [Qimonda AG]

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Internet Data Sheet

Rev. 1.1, 2007-02

3

03062006-H3V1-XJT4

HYB18TC256160AF

256-Mbit Double-Data-Rate-Two SDRAM

1Overview

This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main

characteristics.

1.1

Features

The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:

• 1.8 V

± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18)

compatible I/O

• DRAM organizations with 4, 8 and 16 data in/outputs

• Double-Data-Rate-Two architecture: two data transfers

per clock cycle four internal banks for concurrent operation

• CAS Latency: 3, 4, 5

• Burst Length: 4 and 8

• Differential clock inputs (CK and CK)

• Bi-directional, differential data strobes (DQS and DQS) are

transmitted / received with data. Edge aligned with read

data and center-aligned with write data

• DLL aligns DQ and DQS transitions with clock

•DQS can be disabled for single-ended data strobe

operation

• Commands entered on each positive clock edge, data and

data mask are referenced to both edges of DQS

• Data masks (DM) for write data

• Posted CAS by programmable additive latency for better

command and data bus efficiency

• Off-Chip-Driver impedance adjustment (OCD) and On-

Die-Termination (ODT) for better signal quality

• Auto-Precharge operation for read and write bursts

• Auto-Refresh, Self-Refresh and power saving Power-

Down modes

• Average Refresh Period 7.8

µs at a T

CASE lower than

85 °C, 3.9

µs between 85 °C and 95 °C

• High Temperature Self Refresh Mode is supported

(EMR2 A7)

• Full and reduced Strength Data-Output Drivers

• 1K page size

• Package: PG-TFBGA-84

• RoHS Compliant Products1)

TABLE 1

Performance table for –3S

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Product Type Speed Code

–3S

Unit

Speed Grade

DDR2–667D 5–5–5

—

Max. Clock Frequency

@CL5

f

CK5

333

MHz

@CL4

f

CK4

266

MHz

@CL3

f

CK3

200

MHz

Min. RAS-CAS-Delay

t

RCD

15

ns

Min. Row Precharge Time

t

RP

15

ns

Min. Row Active Time

t

RAS

45

ns

Min. Row Cycle Time

t

RC

60

ns

Similar Part No. - HYB18TC256160AF-3.7

Manufacturer	Part #	Datasheet	Description
Qimonda AG	HYB18TC256160AF-3.7	1Mb / 55P	256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

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