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HYB18L256160BFL-7.5 Datasheet(PDF) 8 Page - Qimonda AG |
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HYB18L256160BFL-7.5 Datasheet(HTML) 8 Page - Qimonda AG |
8 / 58 page Data Sheet Rev. 1.73, 2006-09 8 01302004-CZ2R-J9SE HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.1 Power On and Initialization The Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 3). Operational procedures other than those specified may result in undefined operation. FIGURE 3 Power-Up Sequence and Mode Register Sets 1. At first, device core power ( V DD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD and VDDQ are driven from a single power converter output. Assert and hold CKE and DQM to a HIGH level. 2. After V DD and VDDQ are stable and CKE is HIGH, apply stable clocks. 3. Wait for 200 µs while issuing NOP or DESELECT commands. 4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least t RP period. 5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least t RFC period. 6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode Register, each followed by NOP or DESELECT commands for at least t MRD period; the order in which both registers are programmed is not important. Programming of the Extended Mode Register may be omitted when default values (half drive strength, 4 bank refresh) will be used. Following these steps, the Mobile-RAM is ready for normal operation. |
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