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HYB18L256160BC-7.5 Datasheet(PDF) 11 Page - Qimonda AG |
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HYB18L256160BC-7.5 Datasheet(HTML) 11 Page - Qimonda AG |
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11 / 58 page  Data Sheet Rev. 1.73, 2006-09 11 01302004-CZ2R-J9SE HY[B/E]18L256160B[C/F]L-7.5 256-Mbit Mobile-RAM 2.2.1.2 Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6. 2.2.1.3 Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock edge n + m (for details please refer to the READ command description). 2.2.1.4 Write Burst Mode When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write accesses consist of single data elements only. 2.2.1.5 Extended Mode Register The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. TABLE 7 Extended Mode Register Definition (BA[1:0] = 10B) Field Bits Type Description DS [6:5] w Selectable Drive Strength 00B Full Drive Strength 01B Half Drive Strength (default) Note: All other bit combinations are RESERVED. |
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