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HYS64T32900HDL-3.7-B Datasheet(PDF) 3 Page - Qimonda AG |
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HYS64T32900HDL-3.7-B Datasheet(HTML) 3 Page - Qimonda AG |
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3 / 69 page  HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B SO-DIMM DDR2 SDRAM Module Internet Data Sheet Rev. 1.12, 2007-10 3 03292006-5LTN-QML0 1 Overview This chapter gives an overview of the 200-pin Small-Outline DDR2 SDRAM modules product family and describes its main characteristics. 1.1 Features • 200-Pin PC2-6400, PC2-5300, PC2-4200 and PC2-3200 DDR2 SDRAM memory modules. • 32M × 64, 64M × 64 and 128M × 64 module organization,and 32M × 16, 64M × 8 chip organization • 256MB, 512MB and 1GB modules built with 512-Mbit DDR2 SDRAMs in P-TFBGA-84 and P-TFBGA-60 chipsize packages • Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply • All speed grades faster than DDR2-400 comply with DDR2-400 timing specifications. • Programmable CAS Latencies (3, 4, 5 and 6 ), Burst Length (8 & 4). • Auto Refresh (CBR) and Self Refresh • Auto Refresh for temperatures above 85 °C t REFI = 3.9 µs. • Programmable self refresh rate via EMRS2 setting. • Programmable partial array refresh via EMRS2 settings. • DCC enabling via EMRS2 setting. • All inputs and outputs SSTL_1.8 compatible • Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) • Serial Presence Detect with E2PROM • SO-DIMM Dimensions (nominal): 30 mm high, 67.6 mm wide • Based on standard reference layouts Raw Cards 'A', 'C', and 'E' • RoHS compliant products1) TABLE 1 Performance Table 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. QAG Speed Code –25F –2.5 –3 –3S –3.7 –5 Unit DRAM Speed Grade DDR2 –800D –800E –667C –667D –533C –400B Module Speed Grade PC2 –6400D –6400E –5300C –5300D –4200C –3200B CAS-RCD-RP latencies 5–5–5 6–6–6 4–4–4 5–5–5 4–4–4 3–3–3 t CK Max. Clock Frequency CL3 f CK3 200 200 200 200 200 200 MHz CL4 f CK4 266 266 333 266 266 200 MHz CL5 f CK5 400 333 333 333 266 – MHz CL6 f CK6 –400 – – ––MHz Min. RAS-CAS-Delay t RCD 12.5 1512151515ns Min. Row Precharge Time t RP 12.5 1512151515ns Min. Row Active Time t RAS 45 45 45 45 45 40 ns Min. Row Cycle Time t RC 57.5 6057606055ns |
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