Internet Data Sheet

6

Rev.1.80, 2006-11

07092007-3E44-UTNM

HY[B/E]18M512160BF

512-Mbit DDR Mobile-RAM

Overview

1.4

Pin Definition and Description

Table 4

Pin Description

Ball

Type

Detailed Function

CK, CK

Input

Clock: CK and CK are differential clock inputs. All address and control inputs are

sampled on crossing of the positive edge of CK and negative edge of CK.

CKE

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals,

and device input buffers and output drivers. Taking CKE LOW provides precharge power-

down and self refresh operation (all banks idle), or active power-down (row active in any

bank). CKE must be maintained HIGH throughout read and write accesses. Input buffers,

excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding

CKE are disabled during self refresh.

CS

Input

Chip Select: All commands are masked when CS is registered HIGH. CS provides for

external bank selection on systems with multiple banks. CS is considered part of the

command code

RAS, CAS,

WE

Input

Command Inputs: RAS, CAS and WE (along with CS) define the command being

entered.

DQ0 - DQ15

I/O

Data Inputs/Output: Bi-directional data bus (16 bit)

LDQS, UDQS I/O

Data Strobe: output with read data, input with write data. Edge-aligned with read data,

centered with write data. Used to capture write data.

LDQS corresponds to the data on DQ0 - DQ7; UDQS to the data on DQ8 - DQ15.

LDM, UDM

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH coincident with that input data during a WRITE access. DM is

sampled on both edges of DQS. Although DM pins are input only, the DM loading

matches the DQ and DQS loading.

DM may be driven HIGH, LOW, or floating during READs.

LDM corresponds to the data on DQ0 - DQ7; UDM to the data on DQ8 - DQ15.

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ,

WRITE or PRECHARGE command is being applied. BA0, BA1 also determine which

mode register is to be loaded during a MODE REGISTER SET command (MRS or

EMRS).

A0 - A12

Input

Address Inputs: Provide the row address for ACTIVE commands and the column

address and Auto Precharge bit for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 (=AP) is sampled during a precharge

command to determine whether the PRECHARGE applies to one bank (A10=LOW) or all

banks (A10=HIGH). If only one bank is to be precharged, the bank is selected by BA0

and BA1. The address inputs also provide the op-code during a MODE REGISTER SET

command.

V

DDQ

Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity:

V

V

SSQ

Supply I/O Ground

V

DD

Supply Power Supply: Power for the core logic and input buffers,

V

V

SS

Supply Ground

N.C.

–

No Connect