HYB18TC512160BF-3 datasheet(7/61 Pages) QIMONDA

Part #	HYB18TC512160BF-3

Description	512-Mbit Double-Data-Rate-Two SDRAM

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Manufacturer	QIMONDA [Qimonda AG]

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Internet Data Sheet

Rev. 1.11, 2006-09

7

03292006-HDLH-OAY6

HYB18TC512[16/80]0BF

512-Mbit Double-Data-Rate-Two SDRAM

2

Pin Configuration

This chapter contains the pin configuration tables.

2.1

CPin Configuration for TFBGA–60 TFBGA–84

The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and Buffer Type

columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package is depicted in Figure 1

for

×4, Figure 2 for ×8 and Figure 3 for ×16.

TABLE 6

Pin Configuration of DDR2 SDRAM

Ball#/Pin#

Name

Type

Buffer

Type

Function

Clock Signals

×8 Organization

E8

CK

I

SSTL

Clock Signal CK, Complementary Clock Signal CK

F8

CK

I

SSTL

F2

CKE

I

SSTL

Clock Enable

Clock Signals

×16 Organization

J8

CK

I

SSTL

Clock Signal CK, Complementary Clock Signal CK

K8

CK

I

SSTL

K2

CKE

I

SSTL

Clock Enable

Control Signals

×8 Organization

F7

RAS

I

SSTL

Row Address Strobe (RAS), Column Address Strobe (CAS), Write

Enable (WE)

G7

CAS

I

SSTL

F3

WE

I

SSTL

G8

CS

I

SSTL

Chip Select

Control Signals

×16 Organization

K7

RAS

I

SSTL

Row Address Strobe (RAS), Column Address Strobe (CAS), Write

Enable (WE)

L7

CAS

I

SSTL

K3

WE

I

SSTL

L8

CS

I

SSTL

Chip Select

G2

BA0

I

SSTL

Bank Address Bus 1:0

G3

BA1

I

SSTL

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HYB18TC512160BF-3 Datasheet(PDF) 7 Page - Qimonda AG

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