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HYS64T32000EDL-2.5-B2 Datasheet(PDF) 6 Page - Qimonda AG |
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HYS64T32000EDL-2.5-B2 Datasheet(HTML) 6 Page - Qimonda AG |
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6 / 79 page  HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2 Small Outlined DDR2 SDRAM Modules Internet Data Sheet Rev. 1.13, 2007-10 6 08212006-PKYN-2H1B 2 Pin Configurations 2.1 Pin Configurations The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations used in columns Pin Type and Buffer Type are explained in Table 6 and Table 7 respectively. The Pin numbering is depicted in Figure 1 TABLE 5 Pin Configuration of SO-DIMM Pin No. Name Pin Type Buffer Type Function Clock Signals 30 CK0 I SSTL Clock Signals 1:0, Complement Clock Signals 1:0 The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. 164 CK1 I SSTL 32 CK0 ISSTL 166 CK1 ISSTL 79 CKE0 I SSTL Clock Enable Rank 1:0 Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE LOW initiates the Power Down Mode or the Self Refresh Mode. Note: 2 Ranks module 80 CKE1 I SSTL NC NC — Not Connected Note: 1-rank module Control Signals 110 S0 ISSTL Chip Select Rank 1:0 Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. Ranks are also called "Physical banks".2 Ranks module 115 S1 ISSTL NC NC — Not Connected Note: 1-rank module 108 RAS ISSTL Row Address Strobe When sampled at the cross point of the rising edge of CK, and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. 113 CAS ISSTL Column Address Strobe |
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