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HYB25D512400CT-5 Datasheet(PDF) 7 Page - Qimonda AG |
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HYB25D512400CT-5 Datasheet(HTML) 7 Page - Qimonda AG |
7 / 37 page Internet Data Sheet Rev. 1.31, 2006-09 7 03292006-3TFJ-HNV3 HYB25D512[400/160/800]C[E/T/F/C](L) 512-Mbit Double-Data-Rate SDRAM 2 Pin Configuration The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer# column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the TSOP package in Figure 2 TABLE 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Buffer Type Function Clock Signals G2, 45 CK1 I SSTL Clock Signal G3, 46 CK1 I SSTL Complementary Clock Signal H3, 44 CKE I SSTL Clock Enable Control Signals H7, 23 RAS I SSTL Row Address Strobe G8, 22 CAS I SSTL Column Address Strobe G7, 21 WE I SSTL Write Enable H8, 24 CS I SSTL Chip Select Address Signals J8, 26 BA0 I SSTL Bank Address Bus 2:0 J7, 27 BA1 I SSTL K7, 29 A0 I SSTL Address Bus 11:0 L8, 30 A1 I SSTL L7, 31 A2 I SSTL M8, 32 A3 I SSTL M2, 35 A4 I SSTL L3, 36 A5 I SSTL L2, 37 A6 I SSTL K3, 38 A7 I SSTL K2, 39 A8 I SSTL J3, 40 A9 I SSTL K8, 28 A10 I SSTL AP I SSTL J2, 41 A11 I SSTL H2, 42 A12 I SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies NC NC — Note: Module based on 128 Mbit or smaller dies |
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