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HYB39SC128800FE-6 Datasheet(PDF) 3 Page - Qimonda AG |
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HYB39SC128800FE-6 Datasheet(HTML) 3 Page - Qimonda AG |
3 / 20 page Internet Data Sheet Rev. 1.1, 2007-02 3 09072006-N4GC-EREN HY[B/I]39SC128[800/160]FE 128-MBit Synchronous DRAM 1Overview This chapter lists all main features of the product family HY[B/I]39S128[800/160]FE and the ordering information. 1.1 Features • Fully Synchronous to Positive Clock Edge • 0 to 70 °C Operating Temperature for HYB... • -40 to 85 °C Operating Temperature for HYI... • Four Banks controlled by BA0 & BA1 • Programmable CAS Latency: 2 & 3 • Programmable Wrap Sequence: Sequential or Interleave • Programmable Burst Length: 1, 2, 4, 8 and full page • Multiple Burst Read with Single Write Operation • Automatic and Controlled Precharge Command • Data Mask for Read / Write control ( ×8) • Data Mask for Byte Control ( ×16) • Auto Refresh (CBR) and Self Refresh • Power Down and Clock Suspend Mode • 4096 refresh cycles / 64 ms (15.6 µs) • Random Column Address every CLK (1-N Rule) • Single 3.3 V ± 0.3 V Power Supply • LVTTL Interface • Plastic Packages: PG–TSOPII–54 400 mil width TABLE 1 Performance 1.2 Description The HY[B/I]39S128[800/160]FE are four bank Synchronous DRAM’s organized as 16 MBit ×8 and 8 Mbit ×16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with Qimonda advanced 0.11 µm 128-MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply. All 128-Mbit components are available in PG– TSOPII–54 packages. Product Type Speed Code –6 –7 Unit Speed Grade PC166–333 PC133–222 — Max. Clock Frequency @CL3 f CK3 166 143 MHz t CK3 67ns t AC3 5.4 5.4 ns @CL2 t CK2 7.5 7.5 ns t AC2 5.4 5.4 ns |
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