Internet Data Sheet

Rev. 1.1, 2007-01

3

03062006-JXUK-E7R1

HYB25DC128[800/160]C[E/F]

128-Mbit Double-Data-Rate SDRAM

1Overview

This chapter lists all main features of the product family HYB25DC128[800/160]C[E/F] and the ordering information.

1.1

Features

• Double data rate architecture: two data transfers per clock cycle

• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver

• DQS is edge-aligned with data for reads and is center-aligned with data for writes

• Differential clock inputs

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

• Burst Lengths: 2, 4, or 8

• CAS Latency: 2, 2.5, 3

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• RAS-lockout supported

t

• 15.6

µs Maximum Average Periodic Refresh Interval

• 2.5 V (SSTL_2 compatible) I/O

•

V

•

V

• PG-TFBGA-60 package with 3 depopulated rows (8

• PG-TSOPII-66 package

• Lead- and halogene-free = green product

TABLE 1

Performance

The 128-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing

134,217,728 bits. It is internally configured as a quad-bank DRAM.

The 128-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double

data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock

cycle at the I/O pins. A single read or write access for the 128-Mbit Double-Data-Rate SDRAM effectively consists of a single

2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle

data transfers at the I/O pins.

Part Number Speed Code

–5

–6

Unit

Speed Grade

Component

DDR400B

DDR333

—

Max. Clock Frequency

@CL3

f

CK3

200

166

MHz

@CL2.5

f

CK2.5

166

166

MHz

@CL2

f

CK2

133

133

MHz