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HYB25D128400CC-6 Datasheet(PDF) 3 Page - Qimonda AG

Part # HYB25D128400CC-6
Description  128-Mbit Double-Data-Rate SDRAM
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Manufacturer  QIMONDA [Qimonda AG]
Direct Link  http://www.qimonda.com
Logo QIMONDA - Qimonda AG

HYB25D128400CC-6 Datasheet(HTML) 3 Page - Qimonda AG

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Internet Data Sheet
Rev. 1.6, 2007-02
3
03292006-U5AN-6TI1
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
1Overview
This chapter contains features and the description.
1.1
Features
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 2, 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• RAS-lockout supported
t
RAP = tRCD
•7.8
µs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
V
DDQ = 2.5 V ± 0.2 V (DDR266A, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400)
V
DD = 2.5 V ± 0.2 V (DDR266A, DDR333); VDD = 2.6 V ± 0.1 V (DDR400)
• P(G)-TFBGA-60 package with 3 depopulated rows (8
× 12 mm2)
• P(G)-TSOPII-66 package
• Lead- and halogene-free = green product
TABLE 1
Performance
Part Number Speed Code
–5
–6
–7
Unit
Speed Grade
Component
DDR400B
DDR333
DDR266A
Module
PC3200-3033
PC2700–2533
PC2100-2033
max. Clock Frequency
@CL3
f
CK3
200
166
MHz
@CL2.5
f
CK2.5
166
166
143
MHz
@CL2
f
CK2
133
133
133
MHz


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