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HYB25DC512160BE-5 Datasheet(PDF) 9 Page - Qimonda AG |
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HYB25DC512160BE-5 Datasheet(HTML) 9 Page - Qimonda AG |
9 / 35 page Internet Data Sheet Rev. 1.2, 2007-04 9 04112007-FHBX-O8HD HYB25DC512[80/16]0B[E/F] Double-Data-Rate SDRAM 2.2 Configuration of PG-TFBGA-60 The ball configuration of a DDR SDRAM is listed by function in Table 6. The abbreviations used in the Pin#/Buffer# column are explained in Table 7 and Table 8 respectively. TABLE 6 Ball Configuration Ball#/Pin# Name Pin Type Buffer Type Function Clock Signals G2 CK1 I SSTL Clock Signal G3 CK1 I SSTL Complementary Clock Signal H3 CKE I SSTL Clock Enable Control Signals H7 RAS I SSTL Row Address Strobe G8 CAS I SSTL Column Address Strobe G7 WE I SSTL Write Enable H8 CS I SSTL Chip Select Address Signals J8 BA0 I SSTL Bank Address Bus 2:0 J7 BA1 I SSTL K7 A0 I SSTL Address Bus 12:0 L8 A1 I SSTL L7 A2 I SSTL M8 A3 I SSTL M2 A4 I SSTL L3 A5 I SSTL L2 A6 I SSTL K3 A7 I SSTL K2 A8 I SSTL J3 A9 I SSTL K8 A10 I SSTL AP I SSTL J2 A11 I SSTL H2 A12 I SSTL |
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