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HYB18T512800B2F-2.5 Datasheet(PDF) 3 Page - Qimonda AG |
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HYB18T512800B2F-2.5 Datasheet(HTML) 3 Page - Qimonda AG |
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3 / 69 page  Internet Data Sheet Rev. 1.12, 2007-05 3 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM 1Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O • DRAM organizations with 4, 8 and 16 data in/outputs • Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation • CAS Latency: 3, 4, 5 and 6 • Burst Length: 4 and 8 • Differential clock inputs (CK and CK) • Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data. • DLL aligns DQ and DQS transitions with clock •DQS can be disabled for single-ended data strobe operation • Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS • Data masks (DM) for write data • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver impedance adjustment (OCD) and On- Die-Termination (ODT) for better signal quality. • Auto-Precharge operation for read and write bursts • Auto-Refresh, Self-Refresh and power saving Power- Down modes • Average Refresh Period 7.8 µs at a T CASE lower than 85 °C, 3.9 µs between 85 °C and 95 °C • Programmable self refresh rate via EMRS2 setting • Programmable partial array refresh via EMRS2 settings • DCC enabling via EMRS2 setting • Full and reduced Strength Data-Output Drivers • 1kB page size for ×4 & ×8, 2kB page size for ×16 • Packages: P(G)-TFBGA-60 for ×4 & ×8 components, P(G)-TFBGA-84 for ×16 components • RoHS Compliant Products1) • All Speed grades faster than DDR2–400 comply with DDR2–400 timing specifications when run at a clock rate of 200 MHz. TABLE 1 Performance Table for –25F and –2.5 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Product Type Speed Code –25F –2.5 Unit Speed Grade DDR2–800D 5–5–5 DDR2–800E 6–6–6 — Max. Clock Frequency @CL6 f CK6 400 400 MHz @CL5 f CK5 400 333 MHz @CL4 f CK4 266 266 MHz @CL3 f CK3 200 200 MHz Min. RAS-CAS-Delay t RCD 12.5 15 ns Min. Row Precharge Time t RP 12.5 15 ns Min. Row Active Time t RAS 45 45 ns Min. Row Cycle Time t RC 57.5 60 ns |
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