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HYB18T512160AF-3.7 Datasheet(PDF) 2 Page - Qimonda AG |
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HYB18T512160AF-3.7 Datasheet(HTML) 2 Page - Qimonda AG |
2 / 58 page We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com Internet Data Sheet HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 2 03062006-CPCN-4867 HYB18T512400AF(L), HYB18T512800AF(L), HYB18T512160AF(L) Revision History: 2007-01, Rev. 1.71 Page Subjects (major changes since last revision) All Qimonda update All Adapted internet edition 108 Modified AC Timing Parameters Previous Revision: 2006-05, Rev. 1.7 57 Changed “Read” to “Write” in condition 4. 57 Removed text “Maximum power up interval for V DD / VDDQ is specified As 20.0 ms. The power interval is defined as the amount of time it takes for V DD / VDDQ to power-up From 0 V to 1.8 V ± 100 mV” from condition 1. Previous Revision: 2005-08, Rev. 1.6 |
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