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AKD4126-A Datasheet(PDF) 4 Page - Asahi Kasei Microsystems |
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AKD4126-A Datasheet(HTML) 4 Page - Asahi Kasei Microsystems |
4 / 29 page ASAHI KASEI [AKD4126-A] <KM083203> 2007/01 - 4 - (1)-1-3. Set up SDTI1, SDTI2 and SDTI3 Select input data to SDTI1, SDTI2 and SDTI3 of the AK4126 (U1). When these jumper pins are set to SDTI side, SDTO of the AK4114 (U2) is input to SDTI1, SDTI2 and SDTI3. When these jumper pins are set to GND side, “0” data is input to SDTI1, SDTI2 and SDTI3. (a) “0” data is input to SDTI1 (b) SDTO of the AK4114 (U2) is input to SDTI1 SD T I1 S D T I1 JP 1 J P 1 G N D SD TI SD TI GN D (G N D ) (S D T I) (a) “0” data is input to SDTI2 (b) SDTO of the AK4114 (U2) is input to SDTI2 SD TI2 JP 3 SD TI G ND (G N D ) SD TI2 JP 3 GN D S D T I (S D T I) (a) “0” data is input to SDTI3 (b) SDTO of the AK4114 (U2) is input to SDTI3 SD TI3 S D T I3 JP 5 J P 5 SD TI SD TI G ND G N D (G N D ) (S D T I) (1)-1-4. Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) Set up PLL Mode and Input Audio Interface Format of the AK4126 (U1) by SW1. About setting of default, please refer to Table1. About setting except default, please refer to Table2 and Table3. (1)-1-5. Set up Output Audio Interface Format, Clock Mode and Master Clock Frequency of the AK4114 (U2) Set up Output Audio Interface Format, Clock Mode and Master Clock Frequency of theAK4114 (U2) by SW4. About setting of default, please refer to Table4. About setting except default, please refer to Table5, Table6, and Table7. |
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