 |
 |
|
| W83303AD |
|
|||||||||||||||||
 WINBOND
|
| |||||||||||||||||
|
5 page 
W83303AD/W83303AG Publication Release Date: Jan. 9, 2006 - 3 - Revision 0.52 3. PIN DESCRIPTIONS NO NAME I/O FUNCTION DESCRIPTION 1 S3# I 2 S5# I SYSTEM ACPI CONTROL SIGNALS 3 I2C_DATA I/O 4 I2C_CLK I I2C Interface, and the default ID value are defined as 5CH (0101 110X) as well as 5EH (0101 111X), and X is used to control read/write. 5 RSMRST# OD A signal to indicate 3VDUAL power status. The signal will be issued after 82ms delay when the level of 3VDUAL higher than 2.8V 6 PWM_MODE I 0=Internal RAM for Linear Mode; 1= external RAM for PWM Mode 7 LR3_SEN I 8 LR3_DRV O Linear Regulators ranging form 1.2V to 5V and can be adjusted by external resistors 9 AGND P Power ground 10 5VUSB O 11 5VSBDRV O 12 5VDRV O Power switch for USB devises provides a programmable Voltage (5VDUAL/5VSTR/ 5VCC) for USB devices. It can be set by register CR00 13 3.3V_SEN I 14 3.3VSB_DRV O 3.3VDUAL Voltage regulator 15 VCC3 P Power 3.3Vcc 16 SS I Soft-Start pin. Attach a capacitor to this pin to determine the soft-start rate; and the slew-rate of SS is set by adjust the capacity of the external capacitor. 17 ISET I Attached a specific external resistor to determine the internal reference current. 18 5VSB P Power Pin 19 I_SEN2 I 20 VRAM_DRV2 O 21 VRAM_SEN I 22 I_SEN1 I 23 VRAM_DRV1 O 2 channels of VSTR output for DDR or DDRII with internal current sharing design to balance the current on the channels. In which I_SEN1 & I_SEN2 pins should be connected together to 5VSB or 3VDUAL if only one channel used. The DDR or DDRII determine by DDRDET#. If DDRDET# =0 VRAM=DDR(2.6V) ; DDRDET#=1 VRAM=DDRII(1.8V). 24 AGND P Power ground 25 VRGOOD OD The signal is applied for the Intel® Northwood CPU using; it’s a signal to declare the CPU VID status. |
