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T81L0010A Datasheet(PDF) 11 Page - Taiwan Memory Technology |
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T81L0010A Datasheet(HTML) 11 Page - Taiwan Memory Technology |
11 / 17 page TE CH tm T81L0010A TM Technology Inc. reserves the right P. 11 Publication Date: JAN. 2006 to change products or specifications without notice. Revision:B Special Function Registers a) Interrupt Enable 0 register (ien0) The ien0 register (address : A8) MSB LSB eal wdt et2 es0 et1 ex1 et0 ex0 The ien0 bit functions Bit Symbol Function ien0.6 wdt Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before swdt is set to prevent an unintentional refresh of the watchdog timer. The wdt is reset by hardware 12 instruction cycles after it has been set. Note: other bits are not used to watchdog control The ien0 bit functions b) Interrupt Enable 1 register (ien1) The ien1 register (Address : B8) MSB LSB - swdt pt2 ps pt1 px1 pt0 px0 The ien1 bit functions Bit Symbol Function Ien1.6 swdt Watchdog timer start refresh flag. Set to active/refresh the watchdog timer. When directly set after setting wdt, a watchdog timer refresh is performed. Bit swdt is reset by hardware 12 instruction cycles after it has been set. Pay attention that when write ien1.6, it write the swdt bit, when read ien1.6, we will read out the wdts bit. Ie. Watch dog timer status flag. Set by hardware when the watchdog timer was started. C) Watchdog Timer Reload register (wdtrel) The wdtrel register ( Address : 86 ) MSB LSB 7 6 5 4 3 2 1 0 The wdtrel bit functions Bit Symbol Function wdtrel.7 7 Prescaler select bit. When set, the watchdog is clocked through an additional divide-by-16 prescaler wdtrel.6 t0 wdtrel.0 6-0 Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the wdt when a refresh is triggered by a consecutive setting of bits wdt and swdt The wdtrel register can be loaded and read any time |
Similar Part No. - T81L0010A_06 |
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Similar Description - T81L0010A_06 |
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