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T81L0010A Datasheet(PDF) 10 Page - Taiwan Memory Technology

Part # T81L0010A
Description  8-bit MCU
Download  17 Pages
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Manufacturer  TMT [Taiwan Memory Technology]
Direct Link  http://www.tmtech.com.tw
Logo TMT - Taiwan Memory Technology

T81L0010A Datasheet(HTML) 10 Page - Taiwan Memory Technology

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TE
CH
tm
T81L0010A
TM Technology Inc. reserves the right
P. 10
Publication Date: JAN. 2006
to change products or specifications without notice.
Revision:B
Watchdog Timer
The watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After an external reset the
watchdog timer is disabled and all registers are set to zeros.
Watchdog Timer structure
The watchdog consists of 16-bit counter wdt, reload register wdtrel, prescalers by 2 and by 16 and control logic.
Watchdog block diagram
Start procedure
There are two ways to start the watchdog. One method, called hardware automatic start, is based on examining the level of
signal swd during active internal rst signal. When this condition is met, the watchdog will start running automatically with
default settings (all registers set to zeros).When this criterion is not met during active internal rst signal, a programmer can
start the watchdog later. It will occur when signal swd becomes active. Once the watchdog is started it cannot be stopped
unless internal rst signal becomes active. When wdt registers enters the state 7CFFh , asynchronous wdts signal will become
active. The signal wdts sets the bit 6 in ip0 register and requests reset state. The wdts is cleared either by rst signal or change
of the state of the wdt timer.
Refreshing the watchdog timer
The watchdog timer must be refreshed regularly to prevent reset request signal from becoming active. This requirement
imposes obligation on the programmer to issue two followed instructions. The first instruction sets wdt and the second one
swdt. The maximum allowed delay between settings of the wdt and swdt is 12 clock cycles. While this period has expired
and swdt has not been set, wdt is automatically reset, otherwise the watchdog timer is reloaded with the content of the wdtrel
register and wdt is automatically reset.
/2
/1 6
fc lk /1 2
wd tl
wd th
wd ts
c ontro l
lo g ic
sw d
wd t
sw d t
wd tre l
0
7
81 4
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76


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