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DEVICE INFORMATION

PINOUT

DRVH2

VIN

VREG3

EN2

DRVH1

V5SW

RF

EN1

PGOOD2

SKIPSEL2

CSP2

CSN2

PGOOD1

SKIPSEL1

CSP1

CSN1

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

RHBPACKAGE

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TPS51220

SLVS785 – OCTOBER 2007

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

DRVH1

1

High-side MOSFET gate driver outputs. Source 1.7

Ω, sink 1.0Ω, SW-node referenced floating driver. Drive

O

voltage corresponds to VBST to SW voltage.

DRVH2

24

SW2

25

I/O

High-side MOSFET gate driver returns.

SW1

32

Always alive 3.3V, 10mA Low Dropout Linear Regulator Output. Bypass to (signal) GND with more than 1

μF

VREG3

22

O

ceramic capacitor. Runs from VIN supply or from VREG5 when it is switched over to V5SW input.

EN1

4

Channel 1 and Channel 2 SMPS Enable Pins. When turning on, apply greater than 0.55V and less than 6V.

I

Connect to GND to disable. Adjustable soft-start capacitance to be attached here.

EN2

21

PGOOD1

5

Power Good window comparator outputs for channel 1 and 2. The applied voltage should be less than 6V,

O

and the recommended pull-up resistance value is from 100k

Ω to 1MΩ.

PGOOD2

20

SKIPSEL1

6

Skip Mode Selection pin.

GND: Continuous Conduction Mode

I

VREF2: Auto Skip

SKIPSEL2

19

VREG5: OOA Auto Skip, max 15 skips (suitable for equal to or greater than 400kHz)

CSP1

7

Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should

I/O

be used to extract voltage drop across DCR. 0.1

μF is a good value to start the design. See the current

CSP2

18

sensing scheme section for more details.

CSN1

8

Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the

I

current sense circuit for 5V or higher output voltage setting. Also, used for output discharge terminal.

CSN2

17

VFB1

9

SMPS Voltage Feedback Inputs. Connect the feedback resistors divider, and should be referred to (signal)

I

GND.

VFB2

16

COMP1

10

Loop Compensation Pin for current mode (Error Amplifier Output). Connect R (and C if required) from this

pin to VREF2 for proper loop compensation with current mode operation. Ramp compensation adjustable pin

I

for D-CAP mode, connect R from this pin to VREF2. 10k

Ω is a good value to start the design. 6kΩ to 20kΩ

COMP2

15

can be chosen. See the D-CAP MODE section for more details.

Frequency Setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock

RF

3

I/O

for synchronization.

Copyright © 2007, Texas Instruments Incorporated

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