ASAHI KASEI

[AK5381]

MS0200-E-02

2006/01

- 9 -

SWITCHING CHARACTERISTICS (fs=48kHz

∼ 96kHz)

(Ta=Tmin

∼ Tmax; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 5.5V; C

Parameter

Symbol

min

typ

max

Units

Master Clock Timing

Frequency

Pulse Width Low

Pulse Width High

fCLK

tCLKL

tCLKH

12.288

0.4/fCLK

0.4/fCLK

36.864

MHz

ns

ns

LRCK Frequency

fs

48

96

kHz

Duty Cycle

Slave mode

Master mode

45

50

55

%

%

Audio Interface Timing

Slave mode

SCLK Period

SCLK Pulse Width Low

Pulse Width High

LRCK Edge to SCLK “

↑”

(Note 9)

SCLK “

↑” to LRCK Edge

(Note 9)

LRCK to SDTO (MSB) (Except I

SCLK “

↓” to SDTO

tSCK

tSCKL

tSCKH

tLRSH

tSHLR

tLRS

tSSD

160

65

65

30

30

35

35

ns

ns

ns

ns

ns

ns

ns

Master mode

SCLK Frequency

SCLK Duty

SCLK “

↓” to LRCK

SCLK “

↓” to SDTO

fSCK

dSCK

tMSLR

tSSD

−20

64fs

50

20

35

Hz

%

ns

ns

Reset Timing

PDN Pulse Width

(Note 10)

PDN “

↑” to SDTO valid at Slave Mode

(Note 11)

PDN “

↑” to SDTO valid at Master Mode (Note 11)

tPD

tPDV

tPDV

150

4132

4129

ns

1/fs

1/fs

Note 9. SCLK rising edge must not occur at the same time as LRCK edge.

Note 10. The AK5381 can be reset by bringing the PDN pin = “L”.

Note 11. This cycle is the number of LRCK rising edges from the PDN pin = “H”.