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AK4524 Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AK4524 Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
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8 / 31 page  ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 8 - DIGITAL CHARACTERISTICS (Ta=25 °C; VA, VD=4.75 ∼ 5.25V; VT=2.7 ∼ 5.25V) Parameter Symbol min typ Max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.2 - - - - 0.8 V V High-Level Output Voltage (Iout= −100µA) (Note 10) Low-Level Output Voltage (Iout=100 µA) VOH VOL 2.7 / VT −0.5 - - - - 0.5 V V Input Leakage Current Iin - - ±10 µA Note: 10. Min value is lower voltage of 2.7V or VT −0.5V. SWITCHING CHARACTERISTICS (Ta=25 °C; VA, VD=4.75 ∼ 5.25V, VT=2.7 ∼ 5.25V; C L=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency 11.2896 24.576 MHz External Clock Frequency Pulse Width Low Pulse Width High fCLK tCLKL tCLKH 8.192 0.4/fCLK 0.4/fCLK 49.152 MHz ns ns CLKO Output (X’tal mode) Frequency Duty Cycle fMCK dMCK 11.2896 35 24.576 65 MHz % LRCK Frequency Normal Speed Mode (DFS0=“0”, DFS1=“0”) Double Speed Mode (DFS0=“1”, DFS1=“0”) Quad Speed Mode (DFS0=“0”, DFS1=“1”) fsn fsd fsq 32 64 128 48 96 192 kHz kHz kHz Duty Cycle Slave mode Master mode 45 50 55 % % Audio Interface Timing Slave mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “ ↑” (Note 11) BICK “ ↑” to LRCK Edge (Note 11) LRCK to SDTO (MSB) (Except I 2S mode) BICK “ ↓” to SDTO SDTI Hold Time SDTI Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS 81 33 33 20 20 20 20 40 40 ns ns ns ns ns ns ns ns ns Master mode BICK Frequency BICK Duty BICK “ ↓” to LRCK BICK “ ↓” to SDTO SDTI Hold Time SDTI Setup Time fBCK dBCK tMBLR tBSD tSDH tSDS -20 -20 20 20 64fs 50 20 20 Hz % ns ns ns ns Note 11. BICK rising edge must not occur at the same time as LRCK edge. |
Similar Part No. - AK4524_04 |
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Similar Description - AK4524_04 |
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