W9864G6GH-7 datasheet(17/43 Pages) WINBOND

Part #	W9864G6GH-7

Description	1M 횞 4 BANKS 횞 16 BITS SDRAM

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Manufacturer	WINBOND [Winbond]

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W9864G6GH

Publication Release Date:Aug. 13, 2007

- 17 -

Revision A09

9. These parameters account for the number of clock cycles and depend on the operating frequency

of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count

fractions as whole number)

(1)

tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).

tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).

(2)A.C Latency Characteristics

CKE to clock disable (CKE Latency)

1

tCK

DQM to output to HI-Z (Read DQM Latency)

2

DQM to output to HI-Z (Write DQM Latency)

0

Write command to input data (Write Data Latency)

0

CS to Command input ( CS Latency)

0

Precharge to DQ Hi-Z Lead time

CL = 2

2

CL = 3

3

Precharge to Last Valid data out

CL = 2

1

CL = 3

2

Bust Stop Command to DQ Hi-Z Lead time

CL = 2

2

CL = 3

3

Bust Stop Command to Last Valid Data out

CL = 2

1

CL = 3

2

Read with Auto-precharge Command to Active/Ref Command

CL = 2

BL + tRP

tCK + nS

CL = 3

BL + tRP

Write with Auto-precharge Command to Active/Ref Command

CL = 2

(BL+1) + tRP

CL = 3

(BL+1) + tRP

10. Assumed input rise and fall time (tT ) = 1nS.

If tr & tf is longer than 1nS, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]nS should be added to the parameter

( The

tT maximum can’t be more than 10nS for low frequency application. )

11. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.

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W9864G6GH-7 Datasheet(PDF) 17 Page - Winbond

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