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TMX320DM6437BZDUA Datasheet(PDF) 10 Page - Texas Instruments |
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TMX320DM6437BZDUA Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 309 page  www.ti.com TMS320DM6437 Digital Media Processor SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007 SEE ADDITIONS/MODIFICATIONS/DELETIONS Section 6.20 Section 6.20, Peripheral Component Interconnect (PCI): Table 6-100, PCI External Memory Space Updated/Changed column header from "HEX ADDRESS OFFSET" to "HEX ADDRESS RANGE" Updated/Changed the column header from "REGISTER NAME" to "PCI MASTER WINDOW" Updated/Changed the ending address range from "4xxx xxxx" to "3xxx xxxx" for PCI Master Window 0 through PCI Master Window 31 Section 6.22.2 Section 6.22.2, VLYNQ Electrical Data/Timing: Table 6-108, Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module: Updated/Changed parameter #2, td(VCLKH-TXDV) description to "Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] valid" Table 6-110, RTM RX Data Flop Hold/Setup Timing Constraints: Added RX Data Flop rows 6 and 7. Figure 6-56, VLYNQ Transmit/Receive Timing: Updated/Changed parameter #1, td(VCLKH-TXDI), Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid Section 6.23.2 Section 6.23.2, GPIO Peripheral Input/Output Electrical Data/Timing: Updated/Changed GPIO pin names to "GP[x] input" or "GP[x] output" for clarity 10 Revision History Submit Documentation Feedback |
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