 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SC415MLTRT Datasheet(PDF) 10 Page - Semtech Corporation |
|
||||||||||||||||||||||||||||||
SC415MLTRT Datasheet(HTML) 10 Page - Semtech Corporation |
|
|
10 / 30 page  SC415 10 Once high, DL has a minimum pulse width of typically 330nsec which is the minimum off-time. At the end of the minimum off-time, DL continues to stay high until one of the following occurs: The FB comparator input drops to the 750mV reference, as sensed through the FB pin or the VOUT pin The Zero Cross detector trips, if psave is active The Negative Current Limit detector trips If DL drives low because FB has dropped to 750mV, then another DH on-time is started. This is normal operation at heavy load (fully synchronous operation where either DH or DL is high except during transitions). The Zero Cross detector monitors the voltage across the low-side MOSFET during the DL high time and detects when it reaches zero. If DL drives low because of the Zero Cross detector, and psave is active, then both DH and DL will remain low until FB drops to 750mV, at which point the next DH on-time will begin. If a Zero Cross is detected on eight consecutive cycles, then for each subsequent switching cycle DL will shut off when the Zero Cross detector trips; see the PSAVE Operation section. When this occurs, both DH and DL will stay low until FB drops to 750mV, which will begin the next DH on-time. This is normal operation at light load, (PSAVE Operation, where each cycle consists of a DH pulse, a DL pulse, and dead time with both DH and DL low). The Negative Current Limit detector trips when the drain voltage at the low-side MOSFET reaches +80mV, indicating that a large negative current flows through the inductor from VOUT. When this occurs, DL drives low. Both DH and DL will then stay low until FB drops to 750mV, which will begin the next DH on-time. Tripping Negative Current Limit is rare. To help reduce noise interaction between sides, the rising edge of each DH driver is inhibited momentarily if the other side is switching. For example, if FB2 reaches Applications Information (continued) the 750mV trip point at the same instant that side1 is performing a DH or DL transition (up or down), then side2’s DH driver is held off for roughly 30nsec to allow side1 to finish switching. VOUT Voltage Selection Output voltage is regulated by comparing VOUT as seen through a resistor divider to the internal 750mV reference, see Figure 2. Each output can be adjusted to a voltage between 0.75–5.25V. The output voltage is set by the equation: V OUT = 0.75 × (1 + R1/R2) Figure 2 Note: the parallel resistance of R1 and R2 should not be less than 2kΩ. Using a smaller resistance can cause the IC to default to the internal preset output voltages shown on Page 11. There are fixed output voltages accessible through each FB pin. If the FB pin is connected to either RTN or +5V, then the IC will ignore the FB pin and instead regulate the output voltage using the VOUT pin which is connected to internal resistor divider. Note that each FB input operates independently of the other. + R1 R2 COUT to FB VOUT |
Similar Part No. - SC415MLTRT |
|
Similar Description - SC415MLTRT |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
