 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HT82A851R Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
|
||||||||||||||||||||||||||||||
HT82A851R Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
|
|
11 / 43 page  HT82A851R Rev. 1.20 11 June 15, 2007 If the instruction clock is selected as the WDT clock source, the WDT operates in the same manner except in the halt mode. In the HALT mode, the WDT stops count- ing and lose its protecting purpose. In this situation the logic can only be re-started by external logic. The high nibble of the WDTS is reserved for the DAC write mode. The WDT overflow under normal operation initializes a ²chip reset² and sets the status bit ²TO². In the HALT mode, the overflow initializes a ²warm reset², and only the program counter and stack pointer are reset to zero. To clear the contents of the WDT, there are three meth- ods to be adopted, i.e., an external reset (a low level to RESET), a software instruction, and a ²HALT² instruc- tion. There are two types of software instructions; ²CLR WDT ² and the other set ²CLR WDT1² and ²CLR WDT2 ². Of these two types of instruction, only one type of instruction can be active at a time depending on the configuration option ²CLR WDT² times selection option. If the ²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution of the ²CLR WDT² instruction clears the WDT. In the case that ²CLR WDT1² and ²CLR WDT2 ² are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to a time-out. Power Down Operation - HALT The Power-down mode is entered by the execution of a ²HALT² instruction and results in the following: · The system oscillator will be turned off but the WDT oscillator keeps running if the internal WDT oscillator is selected. · The contents of the on-chip data memory and regis- ters remain unchanged. · The WDT and WDT prescaler will be cleared and will start counting again if the WDT clock is sourced from the internal WDT oscillator. · All of the I/O ports remain in their original condition. · The PDF flag is set and the TO flag is cleared. The system can leave the Power-down mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow performs a ²warm reset². After the TO and PDF flags are examined, the cause for the device reset can be determined. The PDF flag is cleared by a system power-up or by executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the others remain in their original status. A port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each pin in port A can be independently selected to wake-up the device using configuration options. After awakening from an I/O port stimulus, the program will resume execution at the next instruction. If the device is awakened from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to ²1² before entering the Power-down mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock periods) to resume normal operation, i.e., a dummy period is inserted. If the wake-up results from an S y s t e m C l o c k / 4 8 - b i t C o u n t e r W D T P r e s c a l e r 7 - b i t C o u n t e r 8 - t o - 1 M U X W D T T i m e - o u t W S 0 ~ W S 2 M a s k O p t i o n S e l e c t W D T O S C Watchdog Timer Bit No. Label Function 0 1 2 WS0 WS1 WS2 Watchdog Timer division ratio selection bits Bit 2,1,0 = 000, Division Ratio = 1:1 Bit 2,1,0 = 001, Division Ratio = 1:2 Bit 2,1,0 = 010, Division Ratio = 1:4 Bit 2,1,0 = 011, Division Ratio = 1:8 Bit 2,1,0 = 100, Division Ratio = 1:16 Bit 2,1,0 = 101, Division Ratio = 1:32 Bit 2,1,0 = 110, Division Ratio = 1:64 Bit 2,1,0 = 111, Division Ratio = 1:128 3~7 ¾ Unused bit, read as ²0² WDTS (09H) Register |
Similar Part No. - HT82A851R |
|
Similar Description - HT82A851R |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
