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SH3001 MicroBuddy™ SYSTEM MANAGEMENT Copyright ©2002-2005 Semtech Corporation 6 V1.15 www.semtech.com When the HF oscillator is operating alone, it can set the frequency of the clock on the CLKOUT pin to ± 0.025%, and maintain it to ± 0.5% over temperature. This compares favorable with the typical ± 0.5% initial clock accuracy and ± 0.6% overall temperature stability of ceramic resonators. The SH3001 replaces the typical resonator, using less space and providing better performance and functionality. The HF oscillator can also be locked to the internal 32.768 kHz signal. The absolute accuracy and stability of the HF clock depends on the quality of the 32.768 kHz internally generated clock; the low-frequency (LF) Oscillator System is described later in this document. When the Real-Time Clock module of the SH3001 is used for high-accuracy timekeeping, an external 32.768 kHz crystal used as a reference for RTC provides excellent accuracy and stability for the Clock Management System. The SH3001 employs a Frequency Locked Loop (FLL) to synchronize the HF clock to the 32.768 kHz reference. This architecture has several advantages over the common PLL (Phase Locked Loop) systems, including the ability to stop and re-start without frequency transients or instability, and with instant settling to a correct frequency. The conventional PLL approach invariably includes a Low-Pass Filter that requires a long settling time on re-start. The primary purpose of the FLL is the maintenance of the correct frequency while the ambient temperature is changing. As the temperature drift of the HF oscillator is quite small, any corrective action from the FLL system is also small and gradual, commensurate with the temperature variation. The FLL system in the SH3001 is unconditionally stable. To set a new frequency for the FLL, the host processor writes the 13-bit Frequency Set value. The resulting output frequency is calculated using simple formulas [1] and [2] (reference frequency is 32.768 kHz): FOSC = 2048 Hz * (Frequency Set value + 1) [1] FOUT = FOSC / (Post-divider setting) [2] For example, a post-divider setting of ÷8 and the Frequency Set value of 4000 (0x0FA0) produce an output frequency of 1.024 MHz. Programmable Spectrum Spreading Most commercial electronic systems must pass regulatory tests in order to determine the degree of their Electromagnetic Interference (EMI) affecting other electronic devices. In some cases compliance with the EMI standards is costly and complicated. The SH3001 offers a technique for reducing the EMI. It can be a part of the initial design strategy, or it can be applied in the prototype stage to fix problems identified during compliance testing. This feature of the SH3001 can greatly reduce the requirements for radiofrequency shielding, and permits the use of simple plastic casings in place of expensive RFI-coated or metal casings. The SH3001 employs Programmable Spectrum Spreading in order to reduce the RF emissions from the processor’s clock. There are five (5) possible settings; please see Table 1 for operating and performance figures in the 8–16 MHz range. Spectrum Spreading is created by varying the frequency of the HF oscillator with a pseudo-random sequence (with a zero-average DC component). The Maximum-Length Sequence (MLS) 8-bit random number generator, clocked by 32.768 kHz, is used. Only 4, 5, 6, or 7 bits of the generated 8-bit random number are used, according to the configuration setting. Maximum fluctuations of the frequency depend on the selected frequency range and the position within the range. Selecting the HF oscillator frequency to be near the high end of the range limits the peak variations to ± 0.1%, ± 0.2%, ± 0.4%, or ± 0.8% (corresponding to the configuration setting). Table 1. EMI reduction with Spectrum Spreading Setting En CFG1 CFG0 Spreading Bandwidth kHz Peak EMI Reduction (guaranteed) db Peak EMI Reduction (measured) db 0 X X Off 0 0 1 0 0 32 -3 -3 1 0 1 64 -6 -7 1 1 0 128 -9 -10 1 1 1 256 -12 -15 |
