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HT46R64 Datasheet(PDF) 7 Page - Holtek Semiconductor Inc

Part # HT46R64
Description  A/D with LCD Type 8-Bit MCU
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT46R64 Datasheet(HTML) 7 Page - Holtek Semiconductor Inc

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HT46R64/HT46C64
Rev. 1.80
7
February 14, 2006
Functional Description
Execution Flow
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is inter-
nally divided into four non-overlapping clocks. One in-
struction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each in-
struction to be effectively executed in a cycle. If an in-
struction changes the value of the program counter, two
cycles are required to complete the instruction.
Program Counter
- PC
The program counter (PC) is 12 bits wide and it controls
the sequence in which the instructions stored in the pro-
gram ROM are executed. The contents of the PC can
specify a maximum of 4096 addresses.
After accessing a program memory word to fetch an in-
struction code, the value of the PC is incremented by 1.
The PC then points to the memory word containing the
next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading a PCL register, a subroutine call, an ini-
tial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; oth-
erwise proceed to the next instruction.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 )
F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C )
F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
P C
P C + 1
P C + 2
S y s t e m C l o c k
O S C 2 ( R C o n l y )
P C
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
000000000000
External Interrupt 0
000000000100
External Interrupt 1
000000001000
Timer/Event Counter 0 Overflow
000000001100
Timer/Event Counter 1 Overflow
000000010000
Time Base Interrupt
000000010100
RTC Interrupt
000000011000
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
@7~@0: PCL bits


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