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NT5DS32M8CS-5T Datasheet(PDF) 6 Page - NanoAmp Solutions, Inc. |
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NT5DS32M8CS-5T Datasheet(HTML) 6 Page - NanoAmp Solutions, Inc. |
6 / 76 page Block Diagram (32Mb x 8) 1 DQS CK, CK DLL RAS CAS CK CS WE CK Column-Address Counter/Latch Mode 10 A0-A12, BA0, BA1 CKE 15 15 I/O Gating DM Mask Logic Bank0 Memory Array (8192 x 512 x 16) Sense Amplifiers Bank1 Bank2 Bank3 13 9 1 2 2 8 8 8 Input Register 1 1 1 1 1 16 16 2 16 clk out Data Mask Data CK, COL0 COL0 COL0 clk in DQS Generator 8 8 8 8 8 16 DQ0-DQ7, DM DQS 1 Write FIFO & Drivers Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional DQ and DQS signals. Column Decoder 512 (x16) Registers 8192 13 CK NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 6 NanoAmp Solutions, Inc. |
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