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NT5DS32M8CT-5T Datasheet(PDF) 4 Page - NanoAmp Solutions, Inc. |
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NT5DS32M8CT-5T Datasheet(HTML) 4 Page - NanoAmp Solutions, Inc. |
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4 / 76 page  Input/Output Functional Description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer- enced to the crossings of CK and CK (both directions of crossing). CKE, CKE0, CKE1 Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn- chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control of stacked devices. CS, CS0, CS1 Input Chip Select: All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in addition to CS0, to allow upper or lower deck selection on stacked devices. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur- ing a Read, DM can be driven high, low, or floated. BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 - A12 Input Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Pre- charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. DQ Input/Output Data Input/Output: Data bus. DQS, LDQS, UDQS Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0- DQ7; UDQS corresponds to the data on DQ8-DQ15 NC No Connect: No internal electrical connection is present. NU Electrical connection is present. Should not be connected at second level of assembly. VDDQ Supply DQ Power Supply: 2.5V ± 0.2V. VSSQ Supply DQ Ground VDD Supply Power Supply: 2.5V ± 0.2V. VSS Supply Ground VREF Supply SSTL_2 reference voltage: (VDDQ / 2) ± 1%. NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS DOC # 14-02-044 Rev A ECN # 01-1116 The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com 4 NanoAmp Solutions, Inc. |
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