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ADSP-BF561SBBCZ-6A2 Datasheet(PDF) 3 Page - Analog Devices |
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ADSP-BF561SBBCZ-6A2 Datasheet(HTML) 3 Page - Analog Devices |
3 / 64 page ADSP-BF561 Rev. B | Page 3 of 64 | June 2007 GENERAL DESCRIPTION The ADSP-BF561 processor is a high performance member of the Blackfin family of products targeting a variety of multime- dia, industrial, and telecommunications applications. At the heart of this device are two independent Analog Devices Black- fin processors. These Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantage of a clean, orthogonal RISC-like microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities in a single instruction set architecture. The ADSP-BF561 processor has 328K bytes of on-chip memory. Each Blackfin core includes: • 16K bytes of instruction SRAM/cache • 16K bytes of instruction SRAM • 32K bytes of data SRAM/cache • 32K bytes of data SRAM • 4K bytes of scratchpad SRAM Additional on-chip memory peripherals include: • 128K bytes of low latency on-chip L2 SRAM • Four-channel internal memory DMA controller • External memory controller with glueless support for SDRAM, mobile SDRAM, SRAM, and flash. PORTABLE LOW POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances. BLACKFIN PROCESSOR CORE As shown in Figure 2, each Blackfin core contains two multi- plier/accumulators (MACs), two 40-bit ALUs, four video ALUs, and a single shifter. The computational units process 8-bit, 16-bit, or 32-bit data from the register file. Each MAC performs a 16-bit by 16-bit multiply in every cycle, with accumulation to a 40-bit result, providing eight bits of extended precision. The ALUs perform a standard set of arith- metic and logical operations. With two ALUs capable of operating on 16-bit or 32-bit data, the flexibility of the computa- tion units covers the signal processing requirements of a varied set of application needs. Each of the two 32-bit input registers can be regarded as two 16-bit halves, so each ALU can accomplish very flexible single 16-bit arithmetic operations. By viewing the registers as pairs of 16-bit operands, dual 16-bit or single 32-bit operations can be accomplished in a single cycle. By further taking advantage of the second ALU, quad 16-bit operations can be accomplished simply, accelerating the per cycle throughput. The powerful 40-bit shifter has extensive capabilities for per- forming shifting, rotating, normalization, extraction, and depositing of data. The data for the computational units is found in a multiported register file of sixteen 16-bit entries or eight 32-bit entries. A powerful program sequencer controls the flow of instruction execution, including instruction alignment and decoding. The sequencer supports conditional jumps and subroutine calls, as well as zero overhead looping. A loop buffer stores instructions locally, eliminating instruction memory accesses for tight looped code. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from memory. The DAGs share a register file containing four sets of 32-bit Index, Modify, Length, and Base registers. Eight additional 32-bit registers provide pointers for general indexing of variables and stack locations. Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. Level 2 (L2) memories are other memories, on-chip or off-chip, that may take multiple processor cycles to access. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedi- cated scratchpad data memory stores stack and local variable information. At the L2 level, there is a single unified memory space, holding both instructions and data. In addition, half of L1 instruction memory and half of L1 data memory may be configured as either Static RAMs (SRAMs) or caches. The Memory Management Unit (MMU) provides mem- ory protection for individual tasks that may be operating on the core and may protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin instruction set has been optimized so that 16-bit op-codes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit op-codes, representing fully featured multifunction instructions. Blackfin processors sup- port a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been opti- mized for use in conjunction with the VisualDSP C/C++ compiler, resulting in fast and efficient software implementations. |
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