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SC420 Datasheet(PDF) 7 Page - Semtech Corporation |
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SC420 Datasheet(HTML) 7 Page - Semtech Corporation |
7 / 12 page 7 © 2003 Semtech Corp. POWER MANAGEMENT SC420 United States Patent No. 6,441,597 www.semtech.com Applications Information Combi-Sense (Lossless current sense) The Combi-Sense is a way to sense the output current on a combination of power devices. There is no sense resistor and the current is sensed on: Top MOSFET, bot- tom MOSFET and output inductor. An internal phase node VPN sends a signal which is inte- grated by the Combi-Sense network. This network con- sists of a resistor and capacitor in series, connected between VPN and the DRN pins. The resulting signal is large, clean and not duty cycle sensitive. It can be used directly for close loop current mode control and current limit. Fast Switching Drives As the switching frequency of PWM controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP MOSFET) and reduce dead-time (BOTTOM MOSFET) losses. While low Rds_On MOSFET’s present a power saving, the MOSFETs die area is larger and the effective input capacitance of the MOSFET is increased. Often a 50% decrease in Rds_On doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and dead-time losses with a suboptimum driver. While discrete solution can achieve reasonable drive capabil- ity, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe opera- tion can become cumbersome and costly. The SC420 presents a total solution for the high-speed, high power density applications. Wide input supply range of 4.5V- 25V allows use in battery powered applications, new high voltage, distributed power supplies. Shoot Through Protection The control input (CO) to the SC420 is typically supplied by a PWM controller that regulates the power supply out- put. The timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. The shoot-through protection is implemented by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the input supply and ground, a shoot-through condition dur- ing which both the top and bottom FET’s could be on momentarily. The top FET is also prevented from turn- ing on until the bottom FET is off. The top FET turn-on delay is internally set to 20ns (typical) and may be programmably extended by an external capacitor on the Cdelay pin, the delay is increased by 1ns/pf. The EN (enable) pin may be used to turn both TG and BG drives off. This lowers power consumption by reducing the quiescent current draw of the SC420 to IQsd. Tri-State If the CO pin is undriven it will float to an internally de- fined voltage of 1.4V. This will switch the TG and BG pins low and also tri-states the VPN node. Over Temperature Shutdown The SC420 will shutdown by pulling both driver’s low if its junction temperature, T J, exceeds 165°C. The driv- ers will resume operation when T J declines below 155 o C. Layout Guidelines As with any high speed , high current, switching regula- tor circuit, proper layout is critical in achieving optimum performance of the SC420. The Combi-SenseTM Con- troller Evaluation board schematic shows a three-phase synchronous design with all surface mountable compo- nents. Tight placement and short, wide traces must be used in layout of The gate drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the boost supply and adding it to the phase node (DRN) voltage. Since the bootstrap capacitor sup- plies the charge to the top gate, it must be less than 0.5in away from the SC420. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. Supply Voltage The SC420 can operate from 4.75V to 6V. The V IN pin bypass capacitor must also be less than 0.5in away from the SC420. The ground node of this capacitor, the SC420 PGND pin and the Source of the bottom FET must |
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