7

 2004 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC2612E

Having plotted the line ABCD, and confirmed the type of

compensation necessary, compensation component val-

ues can be determined.

At Fco, the line ABCD shows a gain of -27.5dB and a slope

of -20dB/decade. In order for the total open loop gain to

be 0dB with a -20dB/decade slope at this frequency, the

compensated error amp gain at Fco must be +27.5dB

with a 0dB slope. This is the line FG on the plot below.

Since open loop DC gain should be as high as possible to

minimize errors, a zero is placed at F and to minimize

high frequency gain and switching interference a pole is

placed at G.

The zero at F should be no higher than Fco/4 and the

pole at G no lower than 4*Fco. The equations to set the

gain and the pole and zero locations are:

dB)

(in

Fco

at

gain

A

where

gm

Rs

A

=

=

20

10

Rs

Fz

Cs

×

×

p

=

1

2

1

Rs

Fp

Cp

×

×

p

=

1

2

1

For this example, this results in the following values.

W

»

W

=

=

k

k

.

.

Rs

.

30

6

29

8

0

5

27

nF

.

Cs

22

0

10

30

10

25

6

1

3

3

=

×

×

×

×

»

)

rolloff

EA

to

due

y

(unecessar

pF

Cp

14

10

30

10

400

6

1

3

3

=

×

×

×

×

»

Fco

Fz(esr)

Fp(lc)

-60

-40

-20

0

20

40

60

80

100

100.0E+0

1.0E+3

10.0E+3

100.0E+3

1.0E+6

Frequency (Hz)

A

B

C

D

E

F

G

H

Fp1

Fz1

Filter+modulator

+divider gain

Compensated

Error Amp gain

Total open

loop gain

Fig2: Type 2 Error Amplifier Compensation