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U6225B-FPG3 Datasheet(PDF) 8 Page - TEMIC Semiconductors |
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U6225B-FPG3 Datasheet(HTML) 8 Page - TEMIC Semiconductors |
8 / 12 page TELEFUNKEN Semiconductors U6225B Rev. A1: 25.10.1995 8 (12) 3-Wire-Bus Description When the U6225B-B is controlled via 3-wire bus format, then DATA, CLOCK and ENABLE signals are fed into the SDA, SCL and AS/ENA lines respectively. The dia- gram ’3-WIRE-BUS PULSE DIAGRAM’ shows the data format. The data consist of a single word, which contains the programmable divider and switch information. Only during the enable high period the data is clocked into the internal data shift register on the negative clock transi- tion. During enable low periods the clock input is disabled. New data words are only accepted by the inter- nal data latches from the shift register on a negative transition of the enable signal when during the high period of the enable exactly nineteen clock pulses were send. The data sequence and the timing is described in the fol- lowing diagrams. In 3-wire-bus mode pin 11 becomes automatically the Locksignal output. An improved lock detect circuit gen- erates a flag when the loop has attained lock. ’In lock’ is indicated by a low impedance state (on) of the open col- lector output. In 3-wire-bus mode there is always the high charge pump current active. Only in I2C-bus mode the charge pump current can be controlled. The complete PLL function can be disabled by program- ming a normally not used division ratio of zero. This allows the tuner alignment by supplying the tuning volt- age directly through the 30 V supply voltage of the tuner. 3-Wire-Bus Pulse Diagram P5 P7 Ports LSB SDA MSB 15 Bit scaling factor SF SCL AS / ENA P4 4 Bit P6 95 10733 Figure 5. 3-Wire-Bus Timing TH TS TL TT LSB Clock Enable Data TSL TC 95 10734 Figure 6. Parameters Symbol Min. Typ. Unit Set up time TS 2 ms Enable hold time TSL 2 ms Clock width TC 2 ms Enable set up time TL 10 ms Enable between two transmissions TT 10 ms Data hold time TH 2 ms |
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Similar Description - U6225B-FPG3 |
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