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CAT524LI Datasheet(PDF) 7 Page - Catalyst Semiconductor |
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CAT524LI Datasheet(HTML) 7 Page - Catalyst Semiconductor |
7 / 15 page CAT524 © Catalyst Semiconductor, Inc. 7 Doc. No. MD-2006 Rev. G Characteristics subject to change without notice saved may already be resident in the DPP wiper control register. No clock is necessary upon system power-up. The CAT524’s internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. VREF VREF, the voltage applied between pins VREFH and VREFL, sets the configured DPP’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH and VREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. READY/BUSY ¯¯¯¯¯ When saving data to non-volatile memory, the Ready/Busy output (RDY/BSY ¯¯¯¯) signals the start and duration of the non-volatile erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY ¯¯¯¯ goes low and remains low until the programming cycle is complete. During this time the CAT524 will ignore any data appearing at DI and no data will be output on DO. RDY/BSY ¯¯¯¯ is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for non-volatile programming, RDY/BSY ¯¯¯¯ will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT Data is output serially by the CAT524, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 524s to share a single serial data line and simplifies interfacing multiple 524s to a microprocessor. WRITING TO MEMORY Programming the CAT524’s non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP control register via the DI pin. Data enters on the clock’s rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. Programming is achieved by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP wiper control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the non- volatile cells. The CAT524 non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. Figure 1. Writing to Memory D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 1 NEW DPP DATA CURRENT DPP DATA CURRENT DPP VALUE NON-VOL ATILE DPP OUTPUT PROG DO DI CS NEW DPP VALUE VOLATILE NEW DPP VALUE NON-VOL ATILE t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 o RDY/BSY |
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