ESMT

Preliminary

M52S128168A

Elite Semiconductor Memory Technology Inc.

Publication Date: May. 2007

Revision: 1.0

10/47

BA1 BA0 A11 A10

A9

A8 A7

A6

A5 A4

A3

A2 A1 A0

Address bus

1

0

0

0

0

0

0

DS

0

0

PASR

Extended Mode Register Set

A2-A0

WT=0

000

4Bank

001

2 Bank (BankA& BankB) or

(BA1=0)

010

1 Bank (BankA) or

(BA0=BA1=0)

011

R

100

R

101

R

PASR

111

R

A6-A5

Driver Strength

00

Full Strength

01

1/2 Strength

10

1/4 Strength

DS

11

R

Remark R : Reserved

EXTENDED MODE REGISTER SET (EMRS)

The extended mode register stores for selecting PASR;TCSR;DS. The extended mode register set must be done before any active

command after the power up sequence. The extended mode register is written by asserting low on CS,RAS,CAS,WE and high on

BA1,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended more

register). The state of address pins

A0~An in the same cycle as CS,RAS,CAS,WE going low is written in the extended mode register. Refer to the table for specific

codes.

The extended mode register can be changed by using the same command and clock cycle requirements during operations as long

as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks

refreshed.