ESMT

M12S64322A

Elite Semiconductor Memory Technology Inc.

Publication Date: May. 2007

Revision: 1.0

8/46

Version

Parameter

Symbol

-6

-7

Unit

Note

Col. address to col. address delay

1

CLK

3

CAS latency = 3

2

Number of valid

Output data

CAS latency = 2

1

ea

4

Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

AC CHARACTERISTICS

(AC operating condition unless otherwise noted)

-6

-7

Parameter

Symbol

Min

Max

Min

Max

Unit

Note

CAS latency = 3

6

7

CLK cycle time

CAS latency = 2

10

1000

10

1000

ns

1

CAS latency = 3

5.5

6

CLK to valid

output delay

CAS latency = 2

6

6

ns

1,2

CAS latency = 3

2

2

Output data

hold time

CAS latency = 2

2

2

ns

2

CLK high pulsh width

2.5

2.5

ns

3

CLK low pulsh width

2.5

2.5

ns

3

Input setup time

1.5

2

ns

3

Input hold time

1

1

ns

3

CLK to output in Low-Z

1

1

ns

2

CAS latency = 3

5.5

6

CLK to output

in Hi-Z

CAS latency = 2

6

6

ns

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.

3. Assumed input rise and fall time (tr & tf) =1ns.

If tr & tf is longer than 1ns. transient time compensation should be considered.

i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.