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M12L16161A Datasheet(PDF) 11 Page - Elite Semiconductor Memory Technology Inc. |
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M12L16161A Datasheet(HTML) 11 Page - Elite Semiconductor Memory Technology Inc. |
11 / 30 page ESMT M12L16161A Elite Semiconductor Memory Technology Inc. Publication Date : May. 2005 Revision : 2.4 11/30 SIMPLIFIED TRUTH TABLE COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~A0 Note Register Mode Register Set H X L L L L X OP CODE 1,2 Auto Refresh H 3 Entry H L L L L H X X 3 L H H H 3 Refresh Self Refresh Exit L H H X X X X X 3 Bank Active & Row Addr. H X L L H H X V Row Address Auto Precharge Disable L 4 Read & Column Address Auto Precharge Enable H X L H L H X V H Column Address (A0~A7) 4,5 Auto Precharge Disable L 4 Write & Column Address Auto Precharge Enable H X L H L L X V H Column Address (A0~A7) 4,5 Burst Stop H X L H H L X X 6 Bank Selection V L 4 Precharge Both Banks H X L L H L X X H X 4 H X X X Entry H L L V V V X Clock Suspend or Active Power Down Exit L H X X X X X X H X X X Entry H L L H H H X H X X X Precharge Power Down Mode Exit L H L V V V X X DQM H X V X 7 H H X X X No Operation Command H X L H H H X X (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) Note: 1. OP Code: Operation Code A0~ A10/AP, BA: Program keys.(@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”. Auto / self refresh can be issued only at both banks idle state. 4. BA: Bank select address. If “Low”: at read, write, row active and precharge, bank A is selected. If “High”: at read, write, row active and precharge, bank B is selected. If A10/AP is “High” at row precharge, BA ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read /write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) |
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