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F25L008A Datasheet(PDF) 5 Page - Elite Semiconductor Memory Technology Inc. |
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F25L008A Datasheet(HTML) 5 Page - Elite Semiconductor Memory Technology Inc. |
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5 / 31 page  ESMT F25L008A Elite Semiconductor Memory Technology Inc. Publication Date: May. 2007 Revision: 1.4 5/31 47 4KB 02F000H – 02FFFFH : : : 2 32 4KB 020000H – 020FFFH 0 0 1 0 31 4KB 01F000H – 01FFFFH : : : 1 16 4KB 010000H – 010FFFH 0 0 0 1 15 4KB 00F000H – 00FFFFH : : : 0 0 4KB 000000H – 000FFFH 0 0 0 0 Table2 : F25L008A Block Protection Table TOP Status Register Bit Protected Memory Area Protection Level BP2 BP1 BP0 Block Range Address Range 0 0 0 0 None None Upper 1/16 0 0 1 Block 15 F0000H – FFFFFH Upper 1/8 0 1 0 Block 14~15 E0000H – FFFFFH Upper 1/4 0 1 1 Block 12~15 C0000H – FFFFFH Upper 1/2 1 0 0 Block 8~15 80000H – FFFFFH All Blocks 1 0 1 Block 0~15 00000H – FFFFFH All Blocks 1 1 0 Block 0~15 00000H – FFFFFH All Blocks 1 1 1 Block 0~15 00000H – FFFFFH BOTTOM Status Register Bit Protected Memory Area Protection Level BP2 BP1 BP0 Block Range Address Range 0 0 0 0 None None Bottom 1/16 0 0 1 Block 0 00000H – 0FFFFH Bottom 1/8 0 1 0 Block 0~1 00000H – 1FFFFH Bottom 1/4 0 1 1 Block 0~3 00000H – 3FFFFH Bottom 1/2 1 0 0 Block 0~7 00000H – 7FFFFH All Blocks 1 0 1 Block 0~15 00000H – FFFFFH All Blocks 1 1 0 Block 0~15 00000H – FFFFFH All Blocks 1 1 1 Block 0~15 00000H – FFFFFH Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP2, P1, BP0 bits as long as WP is high or the Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1. Block Protection Lock-Down (BPL) WP pin driven low (VIL), enables the Block-Protection -Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the WP pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. |
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