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PPC440EP Datasheet(PDF) 9 Page - Applied Micro Circuits Corporation |
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PPC440EP Datasheet(HTML) 9 Page - Applied Micro Circuits Corporation |
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9 / 84 page  AMCC Proprietary 9 440EP – PPC440EP Embedded Processor Data Sheet Revision 1.26 – April 25, 2007 PowerPC 440 Processor Core The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, etc. It is the first processor core to implement the new Book E PowerPC embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture. Features include: • Up to 667MHz operation • PowerPC Book E architecture • 32KB I-cache, 32KB D-cache – UTLB Word Wide parity on data and tag address parity with exception force • Three logical regions in D-cache: locked, transient, normal • D-cache full line flush capability • 41-bit virtual address, 36-bit (64GB) physical address • Superscalar, out-of-order execution • 7-stage pipeline • 3 execution pipelines • Dynamic branch prediction • Memory management unit – 64-entry, full associative, unified TLB with optional parity – Separate instruction and data micro-TLBs – Storage attributes for write-through, cache-inhibited, guarded, and big or little endian • Debug facilities – Multiple instruction and data range breakpoints – Data value compare – Single step, branch, and trap events – Non-invasive real-time trace interface • 24 DSP instructions – Single cycle multiply and multiply-accumulate – 32 x 32 integer multiply – 16 x 16 -> 32-bit MAC Floating Point Unit (FPU) Features include: • Five stages with 2 MFlops/MHz • Hardware support for IEEE 754 • Single- and double-precision • Single-cycle throughput on most instructions • Thirty-two 64-bit floating point registers |
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