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VRS51C1000-40-Q-ISPV2 Datasheet(PDF) 7 Page - Ramtron International Corporation |
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VRS51C1000-40-Q-ISPV2 Datasheet(HTML) 7 Page - Ramtron International Corporation |
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7 / 48 page  VRS51C1000 ______________________________________________________________________________________________ www.ramtron.com page 7 of 48 VRS51C1000 ISPVx Firmware boot program An ISP boot loader program is available for the VRS51C1000 (ISPVx Firmware, x = revision, see Ramtron website for latest revision). The ISPVx Firmware enables In-System-Programming of the VRS51C1000 on the final application PCB using the device’s UART interface. See the following figure for a hardware configuration example. Other configurations are also possible. FIGURE 4: VRS51C1000 INTERFACE FOR IN-SYSTEM PROGRAMMING VRS51C1000 RXD TXD RES Creset To PC 150k PNP Rreset (with ISPV2 Firmware) See Ramtron’s website in order to download the “Versa Ware ISP” Window’s™ application which allows communication with the ISPVx firmware. The VRS51C1000 can be ordered with or without the ISPVx bootloader firmware (see Ordering information section of this Datasheet for part number information). The ISPVx bootloader firmware can also be programmed into the VRS51C1000 by the user. Source code is included with the Versa Ware ISP application software. For more information on the ISPVx firmware, please consult the “VRS51C1000 ISPVx Firmware User Guide.pdf” available on the Ramtron web site. VRS51C1000 IAP feature The VRS51C1000 IAP feature refers to the ability of the processor to self-program the Flash memory from within the user program. Five SFR registers serve to control the IAP operation. The description of these registers is provided below. System Control Register By default upon reset, the IAP feature of the VRS51C1000 is de-activated. The IAPE bit of the SYSCON register is used to enable (and disable) the VRS51C1000 IAP function. TABLE 6: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH 7 6 5 4 3 2 1 0 WDR Unused IAPE XRAME ALEI Bit Mnemonic Description 7 WDR This is the Watchdog Timer reset bit. It will be set to 1 when the reset signal generated by WDT overflows. 6 Unused - 5 Unused - 4 Unused - 3 Unused - 2 IAPE IAP function enable bit 1 XRAME 768 byte on-chip enable bit 0 ALEI ALE output inhibit bit, which is used to reduce EMI. IAP Flash Address and Data Registers The IAPFADHI and IAPADLO registers are used to specify the address at which the IAP function will be performed. TABLE 7:IAP FLASH ADDRESS HIGH - SFR F4H 7 6 5 4 3 2 1 0 IAPFADHI[15:8] TABLE 8:IAP FLASH ADDRESS LOW - SFR F5H 7 6 5 4 3 2 1 0 IAPFADLO[15:8] The IAPFDATA SFR register contains the Data byte required to perform the IAP function. TABLE 9:IAP FLASH DATA REGISTER - SFR F6H 7 6 5 4 3 2 1 0 IAPFDATA[7:0] IAP Flash Control Register The VRS51C1000 IAP function operation is controlled by the IAP Flash Control register, IAPFCTRL. Setting the IAPSTART bit to 1, starts the execution of the IAP command specified by the IAPFCT[1:0] bits of the IAP Flash Control register. |
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