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VRS51L1050 Datasheet(PDF) 1 Page - Ramtron International Corporation |
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VRS51L1050 Datasheet(HTML) 1 Page - Ramtron International Corporation |
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1 / 49 page  Ramtron International Corporation ♦ http://www.ramtron.com 1850 Ramtron Drive Colorado Springs ♦ MCU customer service: 1-800-943-4625, 1-514-871-2447 x 208 Colorado, USA, 80921 ♦ 1-800-545-FRAM, 1-719-481-7000 page 1 of 49 VRS51L1050 Preliminary Datasheet Rev 1.2 Versa 8051 3.3V MCU with 64KB of IAP/ISP Flash Overview The VRS51L1050 is based on the standard 8051 microcontroller family architecture and is a pin compatible drop-in replacement for most 8051 MCUs. The VRS51L1050 is designed for applications that require a large amount of program/data memory with non-volatile data storage and/or code/field based firmware upgrade capability coupled with comprehensive peripheral support. It features 64KB of In-System/In-Application Programmable Flash memory, 1KB of SRAM, an I²C-compatible interface, 2 PWM output channels, a UART, three 16-bit timers and the ability to exit the power down mode upon assertion of an external interrupt (INT0 / INT1). Ideal for battery-powered applications, the VRS51L1050 registers and I/Os maintain their current value in power down mode while the oscillator is disabled, enabling the supply current to drop below 20uA. The VRS51L1050 is available with firmware that enables In-System Programming (firmware based boot- loader) of the Flash memory via the UART interface (ISPVx version). General Flash memory programming is supported by device programmers available from Ramtron or other 3rd party suppliers. The VRS51L1050 is available in PLCC-44, QFP-44 and DIP-40 packages and functions over the commercial temperature range. FIGURE 1: VRS51L1050 FUNCTIONAL DIAGRAM PORT 0 8051 PROCESSOR PORT 3 PORT 2 PORT 1 PWM PORT 4 64KB FLASH 2 INTERRUPT INPUTS UART 1024 Bytes of SRAM RESET TIMER 0 TIMER 2 TIMER 1 POWER CONTROL ADDRESS/ DATA BUS 8 8 8 8 4 2 I2C Feature Set • 8051/8052 pin compatible • 64KB on-chip Flash memory • In-System/In-Application Flash Programming (ISP/IAP) • On-chip Charge Pump for Flash Programming • 1024 Bytes on-chip Data SRAM • Four 8-bit I/O Ports, one 4-bit I/O Port • 2 PWM Outputs on P1.2 to P1.3 (8/5-bit resolution) • 1 Full Duplex UART Serial Port • I²C-compatible Interface • Three 16-bit Timers/Counters • Bit Operation Instruction • 8-bit Unsigned Division and Multiply • BCD Arithmetic • Direct and Indirect Addressing • 7 Interrupt Sources and 2 Levels of Interrupt Priority • Power saving modes • Wakeup from Power Down by Ext. Interrupt or Reset • Code protection function • Low EMI (inhibit ALE) • Commercial Temperature Range (0°C to +70°C) • 3.3V Operating Voltage FIGURE 2: VRS51L1050 QFP-44 AND PLCC-44 PIN OUT DIAGRAMS 1 44 11 12 22 23 33 34 VRS51L1050 QFP-44 #RD/P3.7 #WR/P3.6 XTAL1 XTAL2 P4.0 VSS P2.1/A9 P2.0/A8 P2.3/A11 P2.2/A10 P2.4/A12 PWM1/P1.3 P1.4 T2EX/P1.1 PWM0/P1.2 P4.2 T2/P1.0 P0.0/AD0 VDD P0.2/AD2 P0.1/AD1 P0.3/AD3 SCL/P1.6 P1.5 RES SDA/P1.7 P4.3 RXD/P3.0 #INT0/P3.2 TXD/P3.1 T0/P3.4 #INT1/P3.3 T1/P3.5 P2.6/A14 P2.5/A13 #PSEN P2.7/A15 P4.1 ALE P0.7/AD7 #EA P0.5/AD5 P0.6/AD6 P0.4/AD4 1 VRS51L1050 PLCC-44 6 7 17 18 28 29 39 40 |
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